Ordinarily, data is transferred from a flip-flop (hereinafter called “FF”) in one clock domain (hereinafter called the transmitter clock domain) and is input to an FF in a different clock domain (hereinafter called the receiver clock domain) in some cases.
In some cases where the FF in the receiver clock domain receives the data, since the data is provided regardless of the clock timing of the FF in the receiver clock domain, setup time or hold time violation and a resultant metastable condition may occur at the output of the FF. In some cases, an effect of the metastable condition is propagated as a difference in logic values to a subsequent FF or combinational logic, and causes an erroneous operation of the semiconductor integrated circuit. Thus, it may verify that the semiconductor integrated circuit is free from an erroneous operation even if a metastable condition occurs.
Logic verification using an ordinary FF model, however, does not take an effect of a metastable condition into account. Thus, there is a known technology for changing a model of a receiver FF that is provided with data transferred from the transmitter clock domain to the receiver clock domain to a model configured to simulate an effect of a metastable condition for performing verification.
Since an effect of the metastable condition is included in a result of the verification performed after the change of the model, it is difficult to analyze a failure factor. Thus, logic verification is usually performed before the change of the model for checking that an ordinary function is free from a problem. Then, a same input pattern is used for logic verification after the change of the model for examining whether the effect of the metastable condition causes no problem. On that occasion, it is important whether or not the input pattern is usable for testing the problem caused by the effect of the metastable condition.
In order to closely estimate whether or not the input pattern is usable enough for testing the problem caused by the effect of the metastable condition, however, it may trace every operation condition in the semiconductor integrated circuit until a change (fluctuation) of the data transferred between the clock domains is propagated to an output terminal of the semiconductor integrated circuit, which may not be dealt with in a practical amount of computation. Thus, a trade-off between accuracy of estimation sufficiency of the input pattern and its computation cost remains a problem to be solved.
If the output terminal of the semiconductor integrated circuit alone is observed, it is unclear a change of data transferred between which clock domains is propagated. Hence, it is made unclear whether or not the input pattern is usable for verifying the metastable condition, and thus there is a problem in that missed verification occurs.
Thus, in lots of cases, a change in data input from the transmitter clock domain to the receiver clock domain alone is observed, and it is identified whether or not the input pattern is usable for testing the problem caused by the effect of the metastable condition. In general, the data transferred from the transmitter clock domain to the receiver clock domain may not be referred to every cycle in the receiver clock domain. At an output of a combinational logic, in some cases where the combinational logic is provided with a plurality of inputs, propagation of an effect of a metastable condition is cut off with an input other than an input to which the effect of the metastable condition is propagated. If only the change in the input data is observed, such a case is not considered and thus there is a problem in that missed verification tends to occur.
Further, according to a technology for performing verification by changing a model of a receiver FF to an FF model that simulates an effect of a metastable condition, a designer (or one who verifies) observes output data of the changed model of the receiver FF, checks how many times the metastable condition occurs and estimates sufficiency of the input pattern. Also in this case, however, a metastable condition that has occurred is referred to, and whether or not the effect is transferred to the later stage is not considered at all. Thus, similarly, there is a problem in that missed verification tends to occur.